1. Field of the Invention
The present invention relates to a voltage generator, more particularly, to a voltage generator which reduces a layout size, reduces a power consumption of a semiconductor device by enhancing a pumping efficiency and a pumping driving ability and generates a cell transistor driving voltage VPP and a substrate bias voltage (called a back bias voltage: VBB).
2. Description of the Prior Art
In general, a cell block of a general DRAM is designed to connect one transistor with one cell capacitor therein. In this case, NMOS transistor is mainly used as the cell transistor because of advantage of area and current driving ability. To read/write a high level data in a cell, a high potential higher than a data potential by a threshold voltage is applied to a gate of a cell transistor. This high potential for driving a cell transistor is called a high voltage VPP, and will now be indicated as a symbol of VPP below.
FIG. 1 is a conventional high voltage generator. As shown in FIG. 1, a detector 10 senses a feedback high voltage VPP level, generates a high voltage pumping enable signal PPE. A ring oscillator 12 functioned as a pump driver receives a high voltage pumping enable signal PPE as an input, and is operated by the high voltage pumping enable signal PPE. A high voltage charge pump unit 14 generates a high voltage VPP by using a coupling capacitor. The high voltage VPP level is fed back to the detector 10, a pumping operation and a pumping stop operation are repeated by the high voltage pumping enable signal PPE, so that the high voltage VPP generator maintains a high voltage VPP level as a desired level.
FIG. 2 is a detailed circuit diagram of the charge pump unit shown in FIG. 1. FIG. 3 is a timing diagram of the charge pump unit shown in FIG. 2. This charge pump unit 14 will be operated as follows.
Referring to FIG. 2, a reference code PL indicates a coupling capacitor driving signal for a high voltage pump at left side of FIG. 2. A reference code pr indicates a coupling capacitor driving signal for a high voltage pump at right side of FIG. 2. A reference code GL indicates a coupling capacitor driving signal for a high voltage pump precharge at left side of FIG. 2. A reference code GR indicates a high voltage pump precharge coupling capacitor driving signal at right side of FIG. 2.
If the high voltage precharge coupling capacitor driving signal GL is changed from a ground potential to a power-supply potential VCC, a node PGL is to be a high level by a coupling capacitor C1 in order to turn on NMOS transistor Ml, thereby precharging a node PPL with a power-supply potential VCC. After that, if the high voltage pump precharge driving signal PL is changed from a ground potential to a power-supply potential VCC, the node PPL rises to a potential 2Vcc by a coupling capacitor C3. At this time, if the high voltage pump coupling capacitor driving signal PR is changed from a power-supply potential VCC to a ground potential and turns on PMOS transistor P1 by a coupling capacitor C4, a high voltage VPP potential rises by a charge sharing between a high voltage VPP node and the node PPL.
In this way, if the power-supply potential VCC is applied to a high voltage pump precharge coupling capacitor driving signal GR, NMOS transistor M2 is turned on by the coupling capacitor C2 to precharge a node PPR with a power-supply potential VCC, the node PPR rises to a potential 2Vcc by the high voltage pump coupling capacitor driving signal PR and the coupling capacitor C4 of a node PPR. After that, if a high voltage pump coupling capacitor driving signal PL is changed from the power-supply potential VCC to a ground potential and PMOS transistor P2 is turned on by a coupling capacitor C3, the high voltage VPP potential rises by a charge sharing between a high voltage VPP node and the node PPR.
By repeating the aforementioned operations, the pumping operations are continued until the high voltage VPP potential level rises to a desired level.
FIG. 4 is a block diagram of a conventional substrate bias voltage generator. Referring to FIG. 4, a detector 16 senses a level of a feedback substrate bias voltage VBB, and generates a substrate bias voltage pumping enable signal BBE. A ring oscillator 18 functioned as a pump driver receives a substrate bias voltage pumping enable signal BBE as an input, and is operated by the substrate bias voltage pumping enable signal BBE. A charge pump unit 20 for a substrate bias voltage generates a substrate bias voltage VBB by using a coupling capacitor. The substrate bias voltage VBB level is fed back again to the detector 16, repeats a pumping operation or non-pumping operation by the substrate voltage pumping enable signal BBE, and thus maintains the substrate bias voltage VBB level to a desired level.
FIG. 5 is a detailed circuit diagram of the charge pump unit 20 shown in FIG. 4, and FIG. 6 is a timing diagram of the circuit shown in FIG. 5. The charge pump unit 20 will be operated as follows.
If a coupling capacitor driving signal GL for a substrate bias voltage pump precharge is changed from a power-supply potential VCC to a ground potential, a node PGL is to be a low level by a coupling capacitor C1 in order to turn on PMOS transistor PM1, thereby precharging a node PPL with a ground potential. After that, if a coupling capacitor driving signal PL for a substrate bias voltage pump is changed from a power-supply potential VCC to a ground potential, the node PPL drops to a potential "-VCC" by a coupling capacitor C3. At this time, if a coupling capacitor driving signal PR for a substrate bias voltage pump is changed from a ground potential to a power-supply potential VCC and turns on NMOS transistor NM1 by a coupling capacitor C4, a substrate bias voltage VBB potential drops by a charge sharing between a substrate bias voltage VBB node and the node PPL.
In this way, if the ground potential is applied to a substrate bias voltage pump precharge coupling capacitor driving signal GR, PMOS transistor PM2 is turned on by the coupling capacitor C2 to precharge a node PPR with a ground potential, the node PPR drops to a potential "-VCC" by the substrate bias voltage pump coupling capacitor driving signal PR and the coupling capacitor C4 of a node PPR. After that, if a substrate bias voltage pump coupling capacitor driving signal PL is changed from the ground potential to the power-supply potential VCC and NMOS transistor NM2 is turned on by a coupling capacitor C3, the substrate bias voltage VBB potential drops by a charge sharing between a substrate bias voltage VBB node and the node PPR.
By repeating the aforementioned operations, the pumping operations are continued until the substrate bias voltage VBB level rises to a desired level.
In this case, fully precharging the nodes PPL and PPR with the ground potential is very important to reduce energy loss. For this purpose, sizes of the precharge transistors PM1 and PM2 should be fully enlarged. In addition, to drive such a large-sized transistor, a precharge coupling capacitor's size should be also enlarged. However, under this condition, a pumping efficiency becomes drop.
A leakage current among DRAM's internal currents is comprised of an off-leakage current and a junction leakage current. A cell leakage current is given much weight in a DRAM having many cell transistors. Particularly, the off-leakage current's percentage is higher than that of others. Following the trend that DRAM is manufactured as a large scale integrated circuit IC and as a high integration IC, the number of cells and the number of cell transistors are increased, and a length of the cell transistor is reduced. Accordingly, a percentage of a leakage of the cell transistors becomes more elevated.